1. Field of the Invention
The present invention relates to a method of pulse programming, in particular for memory devices exhibiting a high parallelism.
The invention also relates to a device implementing the method.
The invention relates, particularly but not exclusively, to a non-volatile memory, and the detailed description that follows will make reference to this field of application for convenience of explanation only.
2. Description of the Related Art
As is well known, in a memory device that uses floating-gate MOS transistors as basic memory cells, the threshold voltage of the floating-gate transistor is modulated in order to discriminate between two logic states, namely: a state where the floating gate contains no charge and that is characteristic of a UV-erased cell (corresponding to a stored logic xe2x80x9c1xe2x80x9d); and a state where the floating gate contains a sufficient number of electrons to raise the threshold level, thus indicating a programmed cell condition (corresponding to a stored logic xe2x80x9c0xe2x80x9d).
To read from a memory cell 1, a current reading method may be used by applying a read voltage Vread to the control gate terminal of the cell and reading the current that flows through the cell:
if the cell is written, its threshold voltage will be higher than the read voltage Vread, and no current is flowing through the cell;
if the cell is erased, its threshold voltage is adequate to allow a current flow.
The probabilistic distribution of the threshold voltages of memory cells, and their digital equivalence, are shown schematically in FIG. 1A for of a two-level EEPROM Flash cell.
To read information from memory cells of this type, a sense amplifier is used to compare the cell current with a reference current value and to convert the analog information of the addressed data contained in the cell (i.e. the threshold voltage value of the cell) into a digital form (i.e. a logic xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d).
Non-volatile multilevel memories have recently made their appearance on the market, these being memories where plural information bits can be stored in each cell. In memories of this kind, the charge contained in the floating gate is further split into a number 2nb of distributions, where xe2x80x9cnbxe2x80x9d is the number of bits to be stored into a single cell. For example, where two bits per cell are provided, the sense amplifier must deal with four distributions instead than two distributions as in the two-level case, as shown schematically in FIG. 1B for a two bits multilevel EEPROM Flash cell.
It should be noted that the working range of the threshold voltage is unrelated to the number of bits that a cell is to contain. Using a multilevel structure involves, therefore, a reduction of the distances separating the various distributions threshold-wise.
Reducing the distances between the threshold voltage distributions means reducing the current differences that the sense amplifier must sense. Moreover, a specific programming method must be used for setting the cells within the different voltage distributions.
The exemplary instance of a NOR architecture Flash EEPROM will be considered here below for simplicity.
As is well known, memory cells of this kind are written by hot electron injection, by applying a 10 V potential to the control gate terminal, a 5 V potential to the drain terminal and by connecting the source terminal to a ground reference, the floating gate terminal is allowed to store charge up to its saturation state.
In a multilevel memory, because of the reduced differences between the threshold voltages that correspond to the various charge levels that the floating gate terminal can accept, and to the differences between the various conduction levels of the cells, the cell programming phase requires a great accuracy control, and especially a control of the charge stored into the floating gate terminal during that programming phase.
It has been shown, both in theory and experimentally, that a linear relation exists between the variation xcex94VG of the voltage applied to the control gate terminal during the cell programming phase and the threshold jump obtained at set values of both the voltage VD applied to the drain terminal and the voltage VS applied to the source terminal, as discussed by Riccò et al. in an article xe2x80x9cNonvolatile Multilevel Memories For Digital Applicationxe2x80x9d, Pro. IEEE, December 1998, vol. 86, pages 2399-2421.
As shown schematically in FIG. 2, the cell should be programmed by applying a linearly increasing voltage to its control gate terminal.
In practice, using a series of program pulses which vary by a constant value xcex94VG is equally advantageous. The programming voltage would be here a constant-pitch stepped ramp.
It can be appreciated that a distribution of the threshold voltage having a width xcex94VG, i.e. the same pitch as the stepped programming voltage, can be obtained by the above programming method.
In that way, multilevel memory cells can be programmed using a desired threshold voltage value and a minimum number of program pulses.
A major problem is that the above cell programming method is inherently a slow one: a succession of pulses must be applied to the control gate terminal of the cell, which takes longer than the single program pulse supplied to two-level cells.
In order to achieve a single byte program time comparable with that of a conventional two-level cell, it has been used programming in parallel several multilevel cells.
If the programming time a single byte is 8 xcexcs in the two-level case, and it takes 200 xcexcs to run the full programming steps in the multilevel case, then an effective programming time of 6 xcexcs per byte in multilevel cells can only be obtained by simultaneously programming 256 bits in multilevel cells.
This results in an increased internal parallelism of multilevel memory devices thus raising problems with their internal configurations.
Well employed by commercially available devices is the synchronous reading mode (burst mode), in order to improve the transfer of data between the memory and the host system. The term xe2x80x9csynchronousxe2x80x9d originates from that the data is to be output synchronously with an external clock signal. The frequency of the clock signal usually exceeds that for the asynchronous access time. The clock signal frequency lies usually in the 50 MHz range, whereas the access time of memory devices is in the 100 ns (10 MHz) range. It""s thus necessary to read internally a much longer binary word than the output word, so as to create a xe2x80x9cbufferxe2x80x9d for different periods of the clock signal.
To increase the size of the internal word means to increase the number of bits that must be read in parallel, and therefore, the number of sense amplifiers in the memory device.
Thus, there is a demand for memory architectures featuring high parallelism at the reading and programming phases. The demand is even more pressing where multilevel memory devices are concerned.
Shown in FIG. 3 is a typical architecture for a non-volatile memory 1. In particular, the memory array comprises a number of sectors 2 divided into two groups, A and B. Each group has a row decoder 3A, 3B and a sense amplifier array 4A, 4B of its own (SA less than 0 greater than  . . . SA less than 7 greater than ).
In the architecture shown, there are eight sense amplifiers, to communicate a binary word of one byte (eight bits) to the outside world. The sense amplifier arrays 4A, 4B are enabled exclusively according to which part (either A or B) of the memory array is to be read or programmed. The digital outputs from the sense amplifiers are passed into a multiplexer 5 for routing to the output pads.
Actually, although there are eight bits to be read, as many as sixteen sense amplifiers have been connected in order to limit the parasitic load seen by them from the bit-line side.
Assume that 64 cells are to be read in parallel. Proceeding by the above technique would be difficult because doubling the number of sense amplifiers means adding as many as 64 elements within the step of two sectors 2; or quadruplicating them within the step of a single sector as shown in FIG. 4.
Thus, the sectorized memory architecture 6 shown in FIG. 4 is used for high-parallelism devices. In this case, each set 4 of sense amplifiers are shared by all the sectors, so that their number can be restricted to 64 and they can be patterned within the step of four sectors.
However, the architecture 6 has an extended bit-line, since the sense amplifiers are located far from the sectors. Also, it comprises a plurality of column decoders 7 connected by a line COLOUT.
In particular, the line COLOUT will take the corresponding outputs from all the column decoders 7 to the relevant sense amplifiers. Each sectors column generates 64 outputs through the column decoder 7, and the line COLOUT connects in particular all the last outputs  less than 63 greater than , as shown in FIG. 4.
A multiplexer (not shown because conventional) is incorporated into the column decoder that must select just the outputs from the sectors column that contains the selected memory location.
It should be noted that, when the sense amplifiers are so distributed and shared by the whole memory array, the bit-lines become of necessity long and introduce significant parasitic capacitance (about 3 to 4 pF for each bit-line) in the memory architecture, taking into account even the line COLOUT connecting the bit-line to its corresponding sense amplifiers.
The increased parasitic load on the bit-line obviously reflects on the sensing circuit and the programming method of the architecture.
In a memory device that is characterized by high parallelism at the programming phase it""s of the utmost importance arranging a strong current draw during the program pulse. This current is to be supplied at constant voltage since the programming phase proceeds by augmenting the voltage at the control gate terminal but maintaining the drain terminal voltage fixed.
FIG. 5 shows generally a bias circuit 10 for the drain terminal of a non-volatile memory cell in schematic form.
The programming voltage VPP may be generated internally using voltage boosters, or supplied by an external supply source.
The bias circuit 10 comprises a drain regulator 11 connected between an output terminal of a programming voltage reference VPP and the drain terminal D of a memory cell CM.
The drain regulator 11 supplies a regulated voltage VPD to a series of enable transistors comprising first PL, second YM, third YN and fourth YO MOS transistors connected between an output terminal O11 of said drain regulator 11 and the drain terminal D of the cell CM.
In particular, the first transistor PL is a P-channel MOS transistor having its source terminal connected to the output terminal O11 of the drain regulator 11 and its drain terminal connected to the line COLOUT of the column decoders, represented here by its capacitive load CPAR1 connected to ground. The first transistor PL is the select transistor, denoted PROGRAM LOAD, and has its gate terminal connected to a first high-voltage switch HVSW1 being applied the regulated voltage VPD and input an enable signal ENABLE_PL_N.
The transistors YM, YN and YO are hierarchic decoder transistors, and have their gate terminals connected to high-voltage switches HVSW2, HVSW3 and HVSW4, respectively; the switches being applied a regulated decoder voltage VPCY and connected to the input of a binary decoder 12. The hierarchic decoder is represented here by its capacitive load CPAR2, which is connected between a circuit node XY, intermediate the decoder transistors YM and YN, and ground GND.
The binary decoder 12 is applied a rated supply voltage VDD to the memory device and is input the column addresses ADDC of the data to be programmed.
It should be noted that the select or program load transistor PL allows the various outputs to be programmed separately, with the regulated voltage VPD being supplied to all the program loads in the memory device. Each Program Load PL has an enable signal ENABLE_PL_N in all cases.
When the regulated voltage VPD is to be taken to the column decoder, the enable signal ENABLE_PL_N of the Program Load PL is brought to a low logic state. The column decoder transistors YM, YN and YO are operated through the high-voltage switches HVSW2, HVSW3 and HVSW4, which are applied the voltage VPCY. During the programming phase, this voltage VPCY is brought approximately to 10 V to minimize the voltage drop across the column decoder.
As to time, the time duration of a single program pulse is on the order of one xcexcs, so that to open a time window of definite width, the drain voltage value of the cell must be switched within 100 ns or less.
In the instance of a multilevel device as discussed above, the time duration of the program pulse and the voltage applied to the cell drain are specially critical parameters to successful programming.
Typically in a ladder programming mode, a memory cell draws a current of several tens xcexcA; assuming a current draw of 50 xcexcA per cell and 64 cells programmed in parallel, it is found that the overall current would be 3.2 mA during the programming phase.
Let us see now in further detail how the single pulse application, a so-called program pulse, is enabled.
For reliability reasons, the value of the cell gate voltage is set first, and the drain voltage is applied next starting with a discharged bit-line. This means that, when the drain terminal of the cell is to be brought to a voltage level of 5 V, the parasitic capacitances CPAR1 and CPASR2 of FIG. 5, i.e. the parasitic capacitances respectively associated with the node COLOUT and the bit-line itself, require to be charged simultaneously.
In a typical instance of 64 lines COLOUT and a total parasitic capacitance (CPAR1+CPAR2) of 4 pF, a total load of 256 pF would have to be charged to 5 V from ground potential during the rising edge of the program pulse. The capacitive charge current, assuming a rising edge of 100 ns and a drain voltage of 5 V, would be given as:             I      charge        =                                        256            *                          10                              -                12                                      *            5                                100            *                          10                              -                9                                                    ⁢        A            =              1.28        ⁢                  xe2x80x83                ⁢        mA              ⁢      xe2x80x83  
In other words, a current is obtained of the same order of magnitude as that actually needed for programming the cells. Obviously, the capacitive load depends on the number of cells. It must be noted that the influence of the capacitive charge current grows inversely as the time allowance for the rise transient of the program pulse.
The combined effects of turning on the cells and charging the parasitic capacitances associated with the bit-lines on the current draw during the transient make it so large that the regulator output voltage is seriously affected. If the regulator cannot be restored to the rated voltage value within 100 ns, or if the node VPP cannot supply the required current, the setting of the program pulse duration becomes less than optimal and significantly dependent on the number of cells to be programmed.
The resultant transient is illustrated by FIG. 6, where the drain terminal of a cell being programmed is shown to quickly attain the value of the regulated voltage VPD; however, that value is reached with a time constant that is proportional to the capacitive load.
Thus, it""s very hard defining this program pulse in the presence of high capacitive loads such that the programming phase can proceed correctly within predetermined time limits.
One object of the present invention is to provide a method of pulse programming memory cells overcoming the foregoing limitations and obviating the shortcomings of the prior art.
An embodiment of the present invention is directed to a pulse programming method for a non-volatile memory device, comprising the steps of:
addressing the memory cells to be programmed in said device by selecting a corresponding program load transistor and a series of hierarchic decoder transistors of a bias circuit;
biasing the gate terminals of said memory cells;
precharging an internal node of said bias circuit connected to a parasitic capacitance of said memory device; and
programming said addressed memory cells by applying a regulated voltage pulse to the drain terminals of said memory cells.
In other words, the method provides a precharging phase of a substantial portion of the parasitic capacitance associated to the bit-line before performing the actual programming phase.
Furthermore, this programming method can be applied to a memory device by modifying the structure of the column decoder drivers, i.e. by modifying the design of the drivers of the column decoder selectors YM to afford switching in a high-voltage and low-consumption condition.
Another embodiment of the invention further relates to a memory device, comprising at least a bias circuit for biasing a drain terminal of non-volatile memory cells and including:
a column decoder portion, connected between a regulated voltage reference and said drain terminal, comprising a program load transistor and a series of hierarchic decoder transistors, all said transistors having their gate terminals connected to respective drive switches;
a parasitic capacitance connected to a common node between said program load transistor and the first of said hierarchic decoder transistors in said column decoder portion;
a binary decoder having a signal input and a plurality of outputs, one for each corresponding drive switches;
a precharge circuit connected between one output of said binary decoder and said first hierarchic decoder transistor and receiving a suitable precharge signal to start a precharge phase of said parasitic capacitance.
The features and advantages of the pulse programming method and the memory device according to the invention will be apparent from the following detailed description of embodiments thereof, given as non-limiting examples with reference to the accompanying drawings.